Re: [PATCH v3 05/20] target/riscv: additional code information for sw check

[Richard Henderson]

On 8/7/24 10:06, Deepak Gupta wrote:
> sw check exception support was recently added. This patch further augments
> sw check exception by providing support for additional code which is
> provided in *tval. Adds `sw_check_code` field in cpuarchstate. Whenever
> sw check exception is raised *tval gets the value deposited in
> `sw_check_code`.
>
> Signed-off-by: Deepak Gupta <debug@rivosinc.com>
> ---
>   target/riscv/cpu.h        | 2 ++
>   target/riscv/cpu_helper.c | 2 ++
>   target/riscv/csr.c        | 1 +
>   3 files changed, 5 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 8c7841fc08..12334f9540 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -224,6 +224,8 @@ struct CPUArchState {
>   
>       /* elp state for zicfilp extension */
>       cfi_elp      elp;
> +    /* sw check code for sw check exception */
> +    target_ulong sw_check_code;

There's probably room for consolidating the different fields
that feed into tval, to be set when raising the exception.

But anyway,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~