Re: [avr-gcc-list] ATmega8515 Interrupt Timing

[Lars Noschinski]

* User Tomdean <address@hidden> [2006-07-29 08:51]:
> Sorry, this is long.
>
> I am trying to match interrupt timimg to ATmega8515 cycles.  I am
> trying to understand the timing and sources of jitter.  I have an
> ATmega8515L with an external 8.000Mhz clock.
>
> My test application has a loop of 4.751usec, or 38 instruction cycles.
> The main loop has 4 instructions for 8 cycles.  The Isr has the
> interrupt latency, *** unknown 1 cycle ***, a preamble of 8 cycles, 3
> instructions for 6 cycles, a post-amble of 7 cycles and an rti of 4
> cycles.

The ISR can only trigger if the current instruction has completed. sbi,
cbi and rjmp take 2 cycles, so if the interrupt triggers, it must
possibly wait a whole additional cycle before it can be executed.