Re: [avr-gcc-list] avr superoptimizer

[Georg-Johann Lay]

Sean D'Epagnier schrieb:

> If I can generate the RTL needed for multiple machines based only on
> the assembly, I will know what gcc is looking for.  Also I can insert
> some kind of profiling or counter into the rtl and later remove all
> the rules gcc never uses.

hmmm. I don't untestand what you mean. You could scan asm generated with 
-dP to get a possible RTL-preimage for some asm instruction sequence. 
Or, of course, use avr.md directly.

> > > Also, that peephole only works for 32bit numbers correct?  What if
> > > there happen to be 2 16 bit ones?  Or even 4 8bit numbers that happen
> > > to be able to benefit from this. Also what if you want to load 0x3bd3
> > > into the upper and lower half using ldi, ldi, movw?  Currently gcc
> > > just does 4 ldis
> >
> > This is no peephole. It is the routine that prints 32-bit mode regs that
> > load zero. Splitting wide types knocks out this function, of course,
> > because that tries to break down SImode to HImode/QImode. I cannot say
> > what happens for 2*HI and if gcc can be driven to reuse regs whose value
> > is known by adapting ome cost functions. In fact, I supplied some
> > patches that will reuse reg contents on SI operations. This can be done
> > for AND, IOR, XOR, CMP, MOV, etc.
> > However, the problem is not to write the optimizations. The problem is
> > that the patches are rotting somewhere in the web because I didn't get a
> > copyright assignment. So no one will ever integrate them in gcc even if
> > they work.
>
> Please send me the patch so I can look at it if you still have it around.

http://lists.gnu.org/archive/html/avr-gcc-list/2009-03/msg00167.html

There are other patches out there like this
   http://lists.gnu.org/archive/html/avr-gcc-list/2009-01/msg00163.html
or that
   http://lists.gnu.org/archive/html/avr-gcc-list/2008-12/msg00019.html

> gcc needs a description for add, and for add with carry.  Then it can
> combine them to for addition for any multiple of 8 bits on avr.  I
> noticed how it did it for 64bit types, and I thought about supporting
> them directly (the same as HI and SI modes).  For fixed point, it
> doesn't even try, it just calls a c function if you don't implement
> it.

gcc knows about add, of course. But how would you write down an 
add-with-carry? Note that this is a PARALLEL that sets two registers, 
one of them fixed with some CCmode. Also note, that you cannot use 
cc_status for that purpose.

With the fixed point modes it is just the same with other unsupported 
modes: gcc will expand them or insert calls to some libs, e.g. libgcc.

Georg-Johann