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[Qemu-devel] [PATCH 042/111] m68k: set X flag according size of operand
From: |
Bryce Lanham |
Subject: |
[Qemu-devel] [PATCH 042/111] m68k: set X flag according size of operand Set X flag correctly for addsub, arith_im, addsubq. |
Date: |
Wed, 17 Aug 2011 15:46:47 -0500 |
From: Laurent Vivier <address@hidden>
Signed-off-by: Laurent Vivier <address@hidden>
---
target-m68k/helper.c | 12 +++++++++++-
target-m68k/helpers.h | 4 +++-
target-m68k/translate.c | 23 ++++++++++++++++-------
3 files changed, 30 insertions(+), 9 deletions(-)
diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index 0fa59c8..451b02a 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -619,7 +619,17 @@ uint32_t HELPER(addx_cc)(CPUState *env, uint32_t op1,
uint32_t op2)
return res;
}
-uint32_t HELPER(xflag_lt)(uint32_t a, uint32_t b)
+uint32_t HELPER(xflag_lt_i8)(uint32_t a, uint32_t b)
+{
+ return (uint8_t)a < (uint8_t)b;
+}
+
+uint32_t HELPER(xflag_lt_i16)(uint32_t a, uint32_t b)
+{
+ return (uint16_t)a < (uint16_t)b;
+}
+
+uint32_t HELPER(xflag_lt_i32)(uint32_t a, uint32_t b)
{
return a < b;
}
diff --git a/target-m68k/helpers.h b/target-m68k/helpers.h
index 76d3063..2e5b8f8 100644
--- a/target-m68k/helpers.h
+++ b/target-m68k/helpers.h
@@ -37,7 +37,9 @@ DEF_HELPER_3(roxr32_cc, i32, env, i32, i32)
DEF_HELPER_3(roxl8_cc, i32, env, i32, i32)
DEF_HELPER_3(roxl16_cc, i32, env, i32, i32)
DEF_HELPER_3(roxl32_cc, i32, env, i32, i32)
-DEF_HELPER_2(xflag_lt, i32, i32, i32)
+DEF_HELPER_2(xflag_lt_i8, i32, i32, i32)
+DEF_HELPER_2(xflag_lt_i16, i32, i32, i32)
+DEF_HELPER_2(xflag_lt_i32, i32, i32, i32)
DEF_HELPER_2(set_sr, void, env, i32)
DEF_HELPER_3(movec, void, env, i32, i32)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 56000eb..f743fd2 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -440,6 +440,15 @@ static inline void gen_flush_flags(DisasContext *s)
} \
} while (0)
+#define SET_X_FLAG(opsize, a, b) do { \
+ switch (opsize) { \
+ case OS_BYTE: gen_helper_xflag_lt_i8(QREG_CC_X, a, b); break; \
+ case OS_WORD: gen_helper_xflag_lt_i16(QREG_CC_X, a, b); break; \
+ case OS_LONG: gen_helper_xflag_lt_i32(QREG_CC_X, a, b); break; \
+ default: abort(); \
+ } \
+} while (0)
+
static void gen_logic_cc(DisasContext *s, TCGv val, int opsize)
{
tcg_gen_mov_i32(QREG_CC_DEST, val);
@@ -1160,10 +1169,10 @@ DISAS_INSN(addsub)
}
if (add) {
tcg_gen_add_i32(dest, tmp, src);
- gen_helper_xflag_lt(QREG_CC_X, dest, src);
+ SET_X_FLAG(opsize, dest, src);
SET_CC_OP(opsize, ADD);
} else {
- gen_helper_xflag_lt(QREG_CC_X, tmp, src);
+ SET_X_FLAG(opsize, tmp, src);
tcg_gen_sub_i32(dest, tmp, src);
SET_CC_OP(opsize, SUB);
}
@@ -1413,7 +1422,7 @@ DISAS_INSN(arith_im)
break;
case 2: /* subi */
tcg_gen_mov_i32(dest, src1);
- gen_helper_xflag_lt(QREG_CC_X, dest, tcg_const_i32(im));
+ SET_X_FLAG(opsize, dest, tcg_const_i32(im));
tcg_gen_subi_i32(dest, dest, im);
gen_update_cc_add(dest, tcg_const_i32(im));
SET_CC_OP(opsize, SUB);
@@ -1422,7 +1431,7 @@ DISAS_INSN(arith_im)
tcg_gen_mov_i32(dest, src1);
tcg_gen_addi_i32(dest, dest, im);
gen_update_cc_add(dest, tcg_const_i32(im));
- gen_helper_xflag_lt(QREG_CC_X, dest, tcg_const_i32(im));
+ SET_X_FLAG(opsize, dest, tcg_const_i32(im));
SET_CC_OP(opsize, ADD);
break;
case 5: /* eori */
@@ -1625,7 +1634,7 @@ DISAS_INSN(neg)
DEST_EA(insn, opsize, dest, &addr);
SET_CC_OP(opsize, SUB);
gen_update_cc_add(dest, src1);
- gen_helper_xflag_lt(QREG_CC_X, tcg_const_i32(0), dest);
+ SET_X_FLAG(opsize, tcg_const_i32(0), dest);
}
static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)
@@ -1920,12 +1929,12 @@ DISAS_INSN(addsubq)
} else {
src2 = tcg_const_i32(val);
if (insn & 0x0100) {
- gen_helper_xflag_lt(QREG_CC_X, dest, src2);
+ SET_X_FLAG(opsize, dest, src2);
tcg_gen_subi_i32(dest, dest, val);
SET_CC_OP(opsize, SUB);
} else {
tcg_gen_addi_i32(dest, dest, val);
- gen_helper_xflag_lt(QREG_CC_X, dest, src2);
+ SET_X_FLAG(opsize, dest, src2);
SET_CC_OP(opsize, ADD);
}
gen_update_cc_add(dest, src2);
--
1.7.2.3
- [Qemu-devel] [PATCH 041/111] mm68k: add nbcd instruction, (continued)
- [Qemu-devel] [PATCH 041/111] mm68k: add nbcd instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 050/111] m68k: lsl/lsr, clear C flag if shift count is 0, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 043/111] m68k: on 0 bit shift, don't update X flag, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 075/111] m68k: better fpu traces, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 062/111] m68k: FPU rework (draft), Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 076/111] m68k: register source operand is always in extended size, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 074/111] m68k: add ftwotox instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 060/111] m68k: remove dead code, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 045/111] m68k: improve subx, negx instructions Add (byte, word) opsize Add memory access (subx), Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 070/111] m68k: initialize FRegs, define pickNaN(), Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 042/111] m68k: set X flag according size of operand Set X flag correctly for addsub, arith_im, addsubq.,
Bryce Lanham <=
- [Qemu-devel] [PATCH 085/111] m68k: add fatan instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 073/111] m68k: add cmpm instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 055/111] m68k: Correct bfclr in register case., Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 054/111] m68k: Added ULL to 64 bit integer in helper.c, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 040/111] m68k: add sbcd instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 082/111] m68k: add fmod instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 068/111] m68k: correct addsubq, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 053/111] m68k: for bitfield opcodes, correct operands corruption, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 057/111] m68k: correctly compute divsl, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 027/111] m68k: add DBcc instruction., Bryce Lanham, 2011/08/17