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[Qemu-devel] [PATCH 073/111] m68k: add cmpm instruction
From: |
Bryce Lanham |
Subject: |
[Qemu-devel] [PATCH 073/111] m68k: add cmpm instruction |
Date: |
Wed, 17 Aug 2011 15:47:18 -0500 |
From: Laurent Vivier <address@hidden>
Allow to run 'flex'.
Signed-off-by: Laurent Vivier <address@hidden>
---
target-m68k/translate.c | 19 +++++++++++++++++++
1 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 1196508..252e610 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -2504,6 +2504,25 @@ DISAS_INSN(eor)
int opsize;
opsize = insn_opsize(insn, 6);
+
+ if (((insn >> 3) & 7) == 1 ) {
+ /* cmpm */
+ reg = AREG(insn, 0);
+ src = gen_load(s, opsize, reg, 1);
+ tcg_gen_addi_i32(reg, reg, opsize_bytes(opsize));
+
+ reg = AREG(insn, 9);
+ dest = gen_load(s, opsize, reg, 1);
+ tcg_gen_addi_i32(reg, reg, opsize_bytes(opsize));
+
+ reg = tcg_temp_new();
+ tcg_gen_sub_i32(reg, dest, src);
+ gen_update_cc_add(reg, src);
+ SET_CC_OP(opsize, SUB);
+
+ return;
+ }
+
SRC_EA(src, opsize, -1, &addr);
reg = DREG(insn, 9);
dest = tcg_temp_new();
--
1.7.2.3
- [Qemu-devel] [PATCH 043/111] m68k: on 0 bit shift, don't update X flag, (continued)
- [Qemu-devel] [PATCH 043/111] m68k: on 0 bit shift, don't update X flag, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 075/111] m68k: better fpu traces, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 062/111] m68k: FPU rework (draft), Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 076/111] m68k: register source operand is always in extended size, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 074/111] m68k: add ftwotox instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 060/111] m68k: remove dead code, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 045/111] m68k: improve subx, negx instructions Add (byte, word) opsize Add memory access (subx), Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 070/111] m68k: initialize FRegs, define pickNaN(), Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 042/111] m68k: set X flag according size of operand Set X flag correctly for addsub, arith_im, addsubq., Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 085/111] m68k: add fatan instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 073/111] m68k: add cmpm instruction,
Bryce Lanham <=
- [Qemu-devel] [PATCH 055/111] m68k: Correct bfclr in register case., Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 054/111] m68k: Added ULL to 64 bit integer in helper.c, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 040/111] m68k: add sbcd instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 082/111] m68k: add fmod instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 068/111] m68k: correct addsubq, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 053/111] m68k: for bitfield opcodes, correct operands corruption, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 057/111] m68k: correctly compute divsl, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 027/111] m68k: add DBcc instruction., Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 083/111] m68k: flush flags before negx instruction., Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 084/111] m68k: correct fmovemx FP registers order., Bryce Lanham, 2011/08/17