Re: [Qemu-devel] [PATCH 15/15] target-tricore: Add instructions of SR opcode format

[Richard Henderson]

On 07/07/2014 11:13 AM, Bastian Koppelmann wrote:
> +static bool cdc_zero(TCState *tc)
> +{
> +    int i;
> +    int cdc = tc->PSW & MASK_PSW_CDC;
> +    /* Returns TRUE if PSW.CDC.COUNT == 0 or if PSW.CDC ==
> +       7'b1111111, otherwise returns FALSE. */
> +    if (cdc == 0x7f) {
> +        return true;
> +    }
> +    /* find CDC.COUNT */
> +    for (i = 7; i > 0; i--) {
> +        if ((cdc & (1 << i)) == 0) {
> +            if ((cdc & ~(0x7f << i)) == 0) {
> +                return true;
> +            }
> +        }
> +    }

Consider using clo32 instead of a loop.

> +static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low)
> +{
> +    TCGv sat_neg = tcg_const_i32(low);
> +    int l1 = gen_new_label();
> +    int l2 = gen_new_label();
> +
> +    /* sat_neg = (arg < low ) ? low : arg; */
> +    tcg_gen_brcondi_tl(TCG_COND_LT, arg, low, l1);
> +    tcg_gen_mov_tl(sat_neg, arg);
> +    gen_set_label(l1);
> +
> +    /* ret = (sat_neg > up ) ? up  : sat_neg; */
> +    tcg_gen_movi_tl(ret, up);
> +    tcg_gen_brcondi_tl(TCG_COND_GT, sat_neg, up, l2);
> +    tcg_gen_mov_tl(ret, sat_neg);
> +    gen_set_label(l2);
> +
> +    tcg_temp_free(sat_neg);
> +}

Again with the movcond.

> +static void gen_rsubi(TCGv ret, int32_t cons, TCGv r2)
> +{
> +    TCGv temp = tcg_temp_new();
> +    tcg_gen_movi_tl(temp, cons);
> +    tcg_gen_sub_tl(ret, temp, r2);
> +    tcg_temp_free(temp);

This is tcg_gen_subfi_tl.

> +/* SR-format jumps */
> +    case OPC1_16_SR_JI:
> +        tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], 0xffffffff);

Huh?  This is a noop.

> +static void decode_sr_system(CPUTRICOREState *env, DisasContext *ctx)
> +{
> +    uint32_t op2;
> +    op2 = MASK_OP_SR_OP2(ctx->opcode);
> +
> +    switch (op2) {
> +    case OPC2_16_SR_NOP:
> +        printf("NOP Instruction at %08x\n", ctx->pc);
> +        ctx->bstate = BS_STOP;

Why stop?

> +    case OPC2_16_SR_RFE:
> +        gen_helper_rfe(cpu_env);
> +        break;

But you do need one here.

> +    case OPC2_16_SR_DEBUG:
> +        printf("DEBUG Instruction at %08x\n", ctx->pc);
> +        ctx->bstate = BS_STOP;

Raise the EXP_DEBUG exception?

> +    case OPC1_16_SR_NOT:
> +        if (MASK_OP_SR_OP2(ctx->opcode) == 0x0) {
> +            printf("Wrong OP2 at at %08x\n", ctx->pc);

You're really going to have to clean up the printfs...


r~