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[PULL 11/29] target/arm: Allow relevant HCR bits to be written for FEAT_
From: |
Peter Maydell |
Subject: |
[PULL 11/29] target/arm: Allow relevant HCR bits to be written for FEAT_EVT |
Date: |
Thu, 15 Dec 2022 12:49:51 +0000 |
FEAT_EVT adds five new bits to the HCR_EL2 register: TTLBIS, TTLBOS,
TICAB, TOCU and TID4. These allow the guest to enable trapping of
various EL1 instructions to EL2. In this commit, add the necessary
code to allow the guest to set these bits if the feature is present;
because the bit is always zero when the feature isn't present we
won't need to use explicit feature checks in the "trap on condition"
tests in the following commits.
Note that although full implementation of the feature (mandatory from
Armv8.5 onward) requires all five trap bits, the ID registers permit
a value indicating that only TICAB, TOCU and TID4 are implemented,
which might be the case for CPUs between Armv8.2 and Armv8.5.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 30 ++++++++++++++++++++++++++++++
target/arm/helper.c | 6 ++++++
2 files changed, 36 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 9aeed3c8481..2b4bd20f9d0 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3757,6 +3757,16 @@ static inline bool isar_feature_aa32_tts2uxn(const
ARMISARegisters *id)
return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0;
}
+static inline bool isar_feature_aa32_half_evt(const ARMISARegisters *id)
+{
+ return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 1;
+}
+
+static inline bool isar_feature_aa32_evt(const ARMISARegisters *id)
+{
+ return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 2;
+}
+
static inline bool isar_feature_aa32_dit(const ARMISARegisters *id)
{
return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0;
@@ -4029,6 +4039,16 @@ static inline bool isar_feature_aa64_ids(const
ARMISARegisters *id)
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) != 0;
}
+static inline bool isar_feature_aa64_half_evt(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 1;
+}
+
+static inline bool isar_feature_aa64_evt(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 2;
+}
+
static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
@@ -4313,6 +4333,16 @@ static inline bool isar_feature_any_ras(const
ARMISARegisters *id)
return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id);
}
+static inline bool isar_feature_any_half_evt(const ARMISARegisters *id)
+{
+ return isar_feature_aa64_half_evt(id) || isar_feature_aa32_half_evt(id);
+}
+
+static inline bool isar_feature_any_evt(const ARMISARegisters *id)
+{
+ return isar_feature_aa64_evt(id) || isar_feature_aa32_evt(id);
+}
+
/*
* Forward to the above feature tests given an ARMCPU pointer.
*/
diff --git a/target/arm/helper.c b/target/arm/helper.c
index d8c8223ec38..751c360ce45 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5267,6 +5267,12 @@ static void do_hcr_write(CPUARMState *env, uint64_t
value, uint64_t valid_mask)
}
}
+ if (cpu_isar_feature(any_evt, cpu)) {
+ valid_mask |= HCR_TTLBIS | HCR_TTLBOS | HCR_TICAB | HCR_TOCU |
HCR_TID4;
+ } else if (cpu_isar_feature(any_half_evt, cpu)) {
+ valid_mask |= HCR_TICAB | HCR_TOCU | HCR_TID4;
+ }
+
/* Clear RES0 bits. */
value &= valid_mask;
--
2.25.1
- [PULL 00/29] target-arm queue, Peter Maydell, 2022/12/15
- [PULL 01/29] hw/arm/virt: Introduce virt_set_high_memmap() helper, Peter Maydell, 2022/12/15
- [PULL 03/29] hw/arm/virt: Introduce variable region_base in virt_set_high_memmap(), Peter Maydell, 2022/12/15
- [PULL 04/29] hw/arm/virt: Introduce virt_get_high_memmap_enabled() helper, Peter Maydell, 2022/12/15
- [PULL 06/29] hw/arm/virt: Add 'compact-highmem' property, Peter Maydell, 2022/12/15
- [PULL 05/29] hw/arm/virt: Improve high memory region address assignment, Peter Maydell, 2022/12/15
- [PULL 07/29] hw/arm/virt: Add properties to disable high memory regions, Peter Maydell, 2022/12/15
- [PULL 02/29] hw/arm/virt: Rename variable size to region_size in virt_set_high_memmap(), Peter Maydell, 2022/12/15
- [PULL 09/29] target/arm: Add Cortex-A55 CPU, Peter Maydell, 2022/12/15
- [PULL 11/29] target/arm: Allow relevant HCR bits to be written for FEAT_EVT,
Peter Maydell <=
- [PULL 10/29] hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement, Peter Maydell, 2022/12/15
- [PULL 12/29] target/arm: Implement HCR_EL2.TTLBIS traps, Peter Maydell, 2022/12/15
- [PULL 13/29] target/arm: Implement HCR_EL2.TTLBOS traps, Peter Maydell, 2022/12/15
- [PULL 15/29] target/arm: Implement HCR_EL2.TID4 traps, Peter Maydell, 2022/12/15
- [PULL 17/29] hw/arm: Convert TYPE_ARM_SMMU to 3-phase reset, Peter Maydell, 2022/12/15
- [PULL 14/29] target/arm: Implement HCR_EL2.TICAB,TOCU traps, Peter Maydell, 2022/12/15
- [PULL 21/29] hw/intc: Convert TYPE_ARM_GICV3_COMMON to 3-phase reset, Peter Maydell, 2022/12/15
- [PULL 19/29] hw/intc: Convert TYPE_ARM_GIC_COMMON to 3-phase reset, Peter Maydell, 2022/12/15
- [PULL 08/29] hw/arm/virt: build SMBIOS 19 table, Peter Maydell, 2022/12/15
- [PULL 29/29] target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator, Peter Maydell, 2022/12/15