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[PULL 13/29] target/arm: Implement HCR_EL2.TTLBOS traps
From: |
Peter Maydell |
Subject: |
[PULL 13/29] target/arm: Implement HCR_EL2.TTLBOS traps |
Date: |
Thu, 15 Dec 2022 12:49:53 +0000 |
For FEAT_EVT, the HCR_EL2.TTLBOS bit allows trapping on EL1
use of TLB maintenance instructions that operate on the
outer shareable domain:
TLBI VMALLE1OS, TLBI VAE1OS, TLBI ASIDE1OS,TLBI VAAE1OS,
TLBI VALE1OS, TLBI VAALE1OS, TLBI RVAE1OS, TLBI RVAAE1OS,
TLBI RVALE1OS, and TLBI RVAALE1OS.
(There are no AArch32 outer-shareable TLB maintenance ops.)
Implement the trapping.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.c | 33 +++++++++++++++++++++++----------
1 file changed, 23 insertions(+), 10 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 475b48750e9..0ec1c3ffbd6 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -373,6 +373,19 @@ static CPAccessResult access_ttlbis(CPUARMState *env,
const ARMCPRegInfo *ri,
return CP_ACCESS_OK;
}
+#ifdef TARGET_AARCH64
+/* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBOS. */
+static CPAccessResult access_ttlbos(CPUARMState *env, const ARMCPRegInfo *ri,
+ bool isread)
+{
+ if (arm_current_el(env) == 1 &&
+ (arm_hcr_el2_eff(env) & (HCR_TTLB | HCR_TTLBOS))) {
+ return CP_ACCESS_TRAP_EL2;
+ }
+ return CP_ACCESS_OK;
+}
+#endif
+
static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t
value)
{
ARMCPU *cpu = env_archcpu(env);
@@ -6753,19 +6766,19 @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
.writefn = tlbi_aa64_rvae1is_write },
{ .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+ .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_rvae1is_write },
{ .name = "TLBI_RVAAE1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 3,
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+ .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_rvae1is_write },
{ .name = "TLBI_RVALE1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 5,
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+ .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_rvae1is_write },
{ .name = "TLBI_RVAALE1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 7,
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+ .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_rvae1is_write },
{ .name = "TLBI_RVAE1", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
@@ -6852,27 +6865,27 @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
static const ARMCPRegInfo tlbios_reginfo[] = {
{ .name = "TLBI_VMALLE1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 0,
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+ .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_vmalle1is_write },
{ .name = "TLBI_VAE1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 1,
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+ .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_vae1is_write },
{ .name = "TLBI_ASIDE1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 2,
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+ .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_vmalle1is_write },
{ .name = "TLBI_VAAE1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 3,
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+ .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_vae1is_write },
{ .name = "TLBI_VALE1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 5,
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+ .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_vae1is_write },
{ .name = "TLBI_VAALE1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 7,
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+ .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_vae1is_write },
{ .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0,
--
2.25.1
- [PULL 03/29] hw/arm/virt: Introduce variable region_base in virt_set_high_memmap(), (continued)
- [PULL 03/29] hw/arm/virt: Introduce variable region_base in virt_set_high_memmap(), Peter Maydell, 2022/12/15
- [PULL 04/29] hw/arm/virt: Introduce virt_get_high_memmap_enabled() helper, Peter Maydell, 2022/12/15
- [PULL 06/29] hw/arm/virt: Add 'compact-highmem' property, Peter Maydell, 2022/12/15
- [PULL 05/29] hw/arm/virt: Improve high memory region address assignment, Peter Maydell, 2022/12/15
- [PULL 07/29] hw/arm/virt: Add properties to disable high memory regions, Peter Maydell, 2022/12/15
- [PULL 02/29] hw/arm/virt: Rename variable size to region_size in virt_set_high_memmap(), Peter Maydell, 2022/12/15
- [PULL 09/29] target/arm: Add Cortex-A55 CPU, Peter Maydell, 2022/12/15
- [PULL 11/29] target/arm: Allow relevant HCR bits to be written for FEAT_EVT, Peter Maydell, 2022/12/15
- [PULL 10/29] hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement, Peter Maydell, 2022/12/15
- [PULL 12/29] target/arm: Implement HCR_EL2.TTLBIS traps, Peter Maydell, 2022/12/15
- [PULL 13/29] target/arm: Implement HCR_EL2.TTLBOS traps,
Peter Maydell <=
- [PULL 15/29] target/arm: Implement HCR_EL2.TID4 traps, Peter Maydell, 2022/12/15
- [PULL 17/29] hw/arm: Convert TYPE_ARM_SMMU to 3-phase reset, Peter Maydell, 2022/12/15
- [PULL 14/29] target/arm: Implement HCR_EL2.TICAB,TOCU traps, Peter Maydell, 2022/12/15
- [PULL 21/29] hw/intc: Convert TYPE_ARM_GICV3_COMMON to 3-phase reset, Peter Maydell, 2022/12/15
- [PULL 19/29] hw/intc: Convert TYPE_ARM_GIC_COMMON to 3-phase reset, Peter Maydell, 2022/12/15
- [PULL 08/29] hw/arm/virt: build SMBIOS 19 table, Peter Maydell, 2022/12/15
- [PULL 29/29] target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator, Peter Maydell, 2022/12/15
- [PULL 22/29] hw/intc: Convert TYPE_KVM_ARM_GICV3 to 3-phase reset, Peter Maydell, 2022/12/15
- [PULL 23/29] hw/intc: Convert TYPE_ARM_GICV3_ITS_COMMON to 3-phase reset, Peter Maydell, 2022/12/15
- [PULL 28/29] hw/misc: Move some arm-related files from specific_ss into softmmu_ss, Peter Maydell, 2022/12/15