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[PULL 15/29] target/arm: Implement HCR_EL2.TID4 traps
From: |
Peter Maydell |
Subject: |
[PULL 15/29] target/arm: Implement HCR_EL2.TID4 traps |
Date: |
Thu, 15 Dec 2022 12:49:55 +0000 |
For FEAT_EVT, the HCR_EL2.TID4 trap allows trapping of the cache ID
registers CCSIDR_EL1, CCSIDR2_EL1, CLIDR_EL1 and CSSELR_EL1 (and
their AArch32 equivalents). This is a subset of the registers
trapped by HCR_EL2.TID2, which includes all of these and also the
CTR_EL0 register.
Our implementation already uses a separate access function for
CTR_EL0 (ctr_el0_access()), so all of the registers currently using
access_aa64_tid2() should also be checking TID4. Make that function
check both TID2 and TID4, and rename it appropriately.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.c | 17 +++++++++--------
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index eee95a42f7f..bac2ea62c44 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1895,11 +1895,12 @@ static void scr_reset(CPUARMState *env, const
ARMCPRegInfo *ri)
scr_write(env, ri, 0);
}
-static CPAccessResult access_aa64_tid2(CPUARMState *env,
- const ARMCPRegInfo *ri,
- bool isread)
+static CPAccessResult access_tid4(CPUARMState *env,
+ const ARMCPRegInfo *ri,
+ bool isread)
{
- if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID2)) {
+ if (arm_current_el(env) == 1 &&
+ (arm_hcr_el2_eff(env) & (HCR_TID2 | HCR_TID4))) {
return CP_ACCESS_TRAP_EL2;
}
@@ -2130,12 +2131,12 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
{ .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
.access = PL1_R,
- .accessfn = access_aa64_tid2,
+ .accessfn = access_tid4,
.readfn = ccsidr_read, .type = ARM_CP_NO_RAW },
{ .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
.access = PL1_RW,
- .accessfn = access_aa64_tid2,
+ .accessfn = access_tid4,
.writefn = csselr_write, .resetvalue = 0,
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
offsetof(CPUARMState, cp15.csselr_ns) } },
@@ -7281,7 +7282,7 @@ static const ARMCPRegInfo ccsidr2_reginfo[] = {
{ .name = "CCSIDR2", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 2,
.access = PL1_R,
- .accessfn = access_aa64_tid2,
+ .accessfn = access_tid4,
.readfn = ccsidr2_read, .type = ARM_CP_NO_RAW },
};
@@ -7581,7 +7582,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.name = "CLIDR", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
.access = PL1_R, .type = ARM_CP_CONST,
- .accessfn = access_aa64_tid2,
+ .accessfn = access_tid4,
.resetvalue = cpu->clidr
};
define_one_arm_cp_reg(cpu, &clidr);
--
2.25.1
- [PULL 04/29] hw/arm/virt: Introduce virt_get_high_memmap_enabled() helper, (continued)
- [PULL 04/29] hw/arm/virt: Introduce virt_get_high_memmap_enabled() helper, Peter Maydell, 2022/12/15
- [PULL 06/29] hw/arm/virt: Add 'compact-highmem' property, Peter Maydell, 2022/12/15
- [PULL 05/29] hw/arm/virt: Improve high memory region address assignment, Peter Maydell, 2022/12/15
- [PULL 07/29] hw/arm/virt: Add properties to disable high memory regions, Peter Maydell, 2022/12/15
- [PULL 02/29] hw/arm/virt: Rename variable size to region_size in virt_set_high_memmap(), Peter Maydell, 2022/12/15
- [PULL 09/29] target/arm: Add Cortex-A55 CPU, Peter Maydell, 2022/12/15
- [PULL 11/29] target/arm: Allow relevant HCR bits to be written for FEAT_EVT, Peter Maydell, 2022/12/15
- [PULL 10/29] hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement, Peter Maydell, 2022/12/15
- [PULL 12/29] target/arm: Implement HCR_EL2.TTLBIS traps, Peter Maydell, 2022/12/15
- [PULL 13/29] target/arm: Implement HCR_EL2.TTLBOS traps, Peter Maydell, 2022/12/15
- [PULL 15/29] target/arm: Implement HCR_EL2.TID4 traps,
Peter Maydell <=
- [PULL 17/29] hw/arm: Convert TYPE_ARM_SMMU to 3-phase reset, Peter Maydell, 2022/12/15
- [PULL 14/29] target/arm: Implement HCR_EL2.TICAB,TOCU traps, Peter Maydell, 2022/12/15
- [PULL 21/29] hw/intc: Convert TYPE_ARM_GICV3_COMMON to 3-phase reset, Peter Maydell, 2022/12/15
- [PULL 19/29] hw/intc: Convert TYPE_ARM_GIC_COMMON to 3-phase reset, Peter Maydell, 2022/12/15
- [PULL 08/29] hw/arm/virt: build SMBIOS 19 table, Peter Maydell, 2022/12/15
- [PULL 29/29] target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator, Peter Maydell, 2022/12/15
- [PULL 22/29] hw/intc: Convert TYPE_KVM_ARM_GICV3 to 3-phase reset, Peter Maydell, 2022/12/15
- [PULL 23/29] hw/intc: Convert TYPE_ARM_GICV3_ITS_COMMON to 3-phase reset, Peter Maydell, 2022/12/15
- [PULL 28/29] hw/misc: Move some arm-related files from specific_ss into softmmu_ss, Peter Maydell, 2022/12/15
- [PULL 25/29] hw/intc: Convert TYPE_KVM_ARM_ITS to 3-phase reset, Peter Maydell, 2022/12/15