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[RFC PATCH 18/43] target/loongarch: Implement vsat
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From: |
Song Gao |
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Subject: |
[RFC PATCH 18/43] target/loongarch: Implement vsat |
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Date: |
Sat, 24 Dec 2022 16:16:08 +0800 |
This patch includes:
- VSAT.{B/H/W/D}[U].
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/disas.c | 9 +++
target/loongarch/helper.h | 9 +++
target/loongarch/insn_trans/trans_lsx.c.inc | 9 +++
target/loongarch/insns.decode | 12 ++++
target/loongarch/lsx_helper.c | 70 +++++++++++++++++++++
5 files changed, 109 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index f50a1051b9..1ae085e192 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1032,3 +1032,12 @@ INSN_LSX(vmod_bu, vvv)
INSN_LSX(vmod_hu, vvv)
INSN_LSX(vmod_wu, vvv)
INSN_LSX(vmod_du, vvv)
+
+INSN_LSX(vsat_b, vv_i)
+INSN_LSX(vsat_h, vv_i)
+INSN_LSX(vsat_w, vv_i)
+INSN_LSX(vsat_d, vv_i)
+INSN_LSX(vsat_bu, vv_i)
+INSN_LSX(vsat_hu, vv_i)
+INSN_LSX(vsat_wu, vv_i)
+INSN_LSX(vsat_du, vv_i)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index e5ee9260ad..fc8044db51 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -387,3 +387,12 @@ DEF_HELPER_4(vmod_bu, void, env, i32, i32, i32)
DEF_HELPER_4(vmod_hu, void, env, i32, i32, i32)
DEF_HELPER_4(vmod_wu, void, env, i32, i32, i32)
DEF_HELPER_4(vmod_du, void, env, i32, i32, i32)
+
+DEF_HELPER_4(vsat_b, void, env, i32, i32, i32)
+DEF_HELPER_4(vsat_h, void, env, i32, i32, i32)
+DEF_HELPER_4(vsat_w, void, env, i32, i32, i32)
+DEF_HELPER_4(vsat_d, void, env, i32, i32, i32)
+DEF_HELPER_4(vsat_bu, void, env, i32, i32, i32)
+DEF_HELPER_4(vsat_hu, void, env, i32, i32, i32)
+DEF_HELPER_4(vsat_wu, void, env, i32, i32, i32)
+DEF_HELPER_4(vsat_du, void, env, i32, i32, i32)
diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc
b/target/loongarch/insn_trans/trans_lsx.c.inc
index 2d12470a0b..09924343b2 100644
--- a/target/loongarch/insn_trans/trans_lsx.c.inc
+++ b/target/loongarch/insn_trans/trans_lsx.c.inc
@@ -303,3 +303,12 @@ TRANS(vmod_bu, gen_vvv, gen_helper_vmod_bu)
TRANS(vmod_hu, gen_vvv, gen_helper_vmod_hu)
TRANS(vmod_wu, gen_vvv, gen_helper_vmod_wu)
TRANS(vmod_du, gen_vvv, gen_helper_vmod_du)
+
+TRANS(vsat_b, gen_vv_i, gen_helper_vsat_b)
+TRANS(vsat_h, gen_vv_i, gen_helper_vsat_h)
+TRANS(vsat_w, gen_vv_i, gen_helper_vsat_w)
+TRANS(vsat_d, gen_vv_i, gen_helper_vsat_d)
+TRANS(vsat_bu, gen_vv_i, gen_helper_vsat_bu)
+TRANS(vsat_hu, gen_vv_i, gen_helper_vsat_hu)
+TRANS(vsat_wu, gen_vv_i, gen_helper_vsat_wu)
+TRANS(vsat_du, gen_vv_i, gen_helper_vsat_du)
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index cbd955a9e9..cae67533fd 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -498,7 +498,10 @@ dbcl 0000 00000010 10101 ...............
@i15
#
@vv .... ........ ..... ..... vj:5 vd:5 &vv
@vvv .... ........ ..... vk:5 vj:5 vd:5 &vvv
+@vv_ui3 .... ........ ..... .. imm:3 vj:5 vd:5 &vv_i
+@vv_ui4 .... ........ ..... . imm:4 vj:5 vd:5 &vv_i
@vv_ui5 .... ........ ..... imm:5 vj:5 vd:5 &vv_i
+@vv_ui6 .... ........ .... imm:6 vj:5 vd:5 &vv_i
@vv_i5 .... ........ ..... imm:s5 vj:5 vd:5 &vv_i
vadd_b 0111 00000000 10100 ..... ..... ..... @vvv
@@ -756,3 +759,12 @@ vmod_bu 0111 00001110 01100 ..... ..... .....
@vvv
vmod_hu 0111 00001110 01101 ..... ..... ..... @vvv
vmod_wu 0111 00001110 01110 ..... ..... ..... @vvv
vmod_du 0111 00001110 01111 ..... ..... ..... @vvv
+
+vsat_b 0111 00110010 01000 01 ... ..... ..... @vv_ui3
+vsat_h 0111 00110010 01000 1 .... ..... ..... @vv_ui4
+vsat_w 0111 00110010 01001 ..... ..... ..... @vv_ui5
+vsat_d 0111 00110010 0101 ...... ..... ..... @vv_ui6
+vsat_bu 0111 00110010 10000 01 ... ..... ..... @vv_ui3
+vsat_hu 0111 00110010 10000 1 .... ..... ..... @vv_ui4
+vsat_wu 0111 00110010 10001 ..... ..... ..... @vv_ui5
+vsat_du 0111 00110010 1001 ...... ..... ..... @vv_ui6
diff --git a/target/loongarch/lsx_helper.c b/target/loongarch/lsx_helper.c
index 99bdf4eb02..62ab14051e 100644
--- a/target/loongarch/lsx_helper.c
+++ b/target/loongarch/lsx_helper.c
@@ -1710,3 +1710,73 @@ DO_HELPER_VVV(vmod_bu, 8, helper_vvv, do_vmod_u)
DO_HELPER_VVV(vmod_hu, 16, helper_vvv, do_vmod_u)
DO_HELPER_VVV(vmod_wu, 32, helper_vvv, do_vmod_u)
DO_HELPER_VVV(vmod_du, 64, helper_vvv, do_vmod_u)
+
+static int64_t sat_s(int64_t s1, uint32_t imm)
+{
+ int64_t max = MAKE_64BIT_MASK(0, imm);
+ int64_t min = MAKE_64BIT_MASK(imm, 64);
+
+ if (s1 > max -1) {
+ return max;
+ } else if (s1 < - max) {
+ return min;
+ } else {
+ return s1;
+ }
+}
+
+static void do_vsat_s(vec_t *Vd, vec_t *Vj, uint32_t imm, int bit, int n)
+{
+ switch (bit) {
+ case 8:
+ Vd->B[n] = sat_s(Vj->B[n], imm);
+ break;
+ case 16:
+ Vd->H[n] = sat_s(Vj->H[n], imm);
+ break;
+ case 32:
+ Vd->W[n] = sat_s(Vj->W[n], imm);
+ break;
+ case 64:
+ Vd->D[n] = sat_s(Vj->D[n], imm);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static uint64_t sat_u(uint64_t u1, uint32_t imm)
+{
+ uint64_t umax_imm = MAKE_64BIT_MASK(0, imm + 1);
+
+ return u1 < umax_imm ? u1 : umax_imm;
+}
+
+static void do_vsat_u(vec_t *Vd, vec_t *Vj, uint32_t imm, int bit, int n)
+{
+ switch (bit) {
+ case 8:
+ Vd->B[n] = sat_u((uint8_t)Vj->B[n], imm);
+ break;
+ case 16:
+ Vd->H[n] = sat_u((uint16_t)Vj->H[n], imm);
+ break;
+ case 32:
+ Vd->W[n] = sat_u((uint32_t)Vj->W[n], imm);
+ break;
+ case 64:
+ Vd->D[n] = sat_u((uint64_t)Vj->D[n], imm);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+DO_HELPER_VV_I(vsat_b, 8, helper_vv_i, do_vsat_s)
+DO_HELPER_VV_I(vsat_h, 16, helper_vv_i, do_vsat_s)
+DO_HELPER_VV_I(vsat_w, 32, helper_vv_i, do_vsat_s)
+DO_HELPER_VV_I(vsat_d, 64, helper_vv_i, do_vsat_s)
+DO_HELPER_VV_I(vsat_bu, 8, helper_vv_i, do_vsat_u)
+DO_HELPER_VV_I(vsat_hu, 16, helper_vv_i, do_vsat_u)
+DO_HELPER_VV_I(vsat_wu, 32, helper_vv_i, do_vsat_u)
+DO_HELPER_VV_I(vsat_du, 64, helper_vv_i, do_vsat_u)
--
2.31.1
- [RFC PATCH 38/43] target/loongarch: Implement vbitsel vset, (continued)
- [RFC PATCH 38/43] target/loongarch: Implement vbitsel vset, Song Gao, 2022/12/24
- [RFC PATCH 35/43] target/loongarch: Implement LSX fpu fcvt instructions, Song Gao, 2022/12/24
- [RFC PATCH 39/43] target/loongarch: Implement vinsgr2vr vpickve2gr vreplgr2vr, Song Gao, 2022/12/24
- [RFC PATCH 41/43] target/loongarch: Implement vilvl vilvh vextrins vshuf, Song Gao, 2022/12/24
- [RFC PATCH 42/43] target/loongarch: Implement vld vst, Song Gao, 2022/12/24
- [RFC PATCH 43/43] target/loongarch: Implement vldi, Song Gao, 2022/12/24
- [RFC PATCH 18/43] target/loongarch: Implement vsat,
Song Gao <=
- [RFC PATCH 19/43] target/loongarch: Implement vexth, Song Gao, 2022/12/24
- [RFC PATCH 31/43] target/loongarch: Implement vpcnt, Song Gao, 2022/12/24
- [RFC PATCH 22/43] target/loongarch: Implement LSX logic instructions, Song Gao, 2022/12/24
- [RFC PATCH 15/43] target/loongarch: Implement vmul/vmuh/vmulw{ev/od}, Song Gao, 2022/12/24
- [RFC PATCH 12/43] target/loongarch: Implement vabsd, Song Gao, 2022/12/24
- [RFC PATCH 10/43] target/loongarch: Implement vaddw/vsubw, Song Gao, 2022/12/24