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| From: | Richard Henderson |
| Subject: | Re: [RFC PATCH 22/43] target/loongarch: Implement LSX logic instructions |
| Date: | Sat, 24 Dec 2022 10:34:11 -0800 |
| User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 |
On 12/24/22 00:16, Song Gao wrote:
+TRANS(vand_v, gen_vvv, gen_helper_vand_v) +TRANS(vor_v, gen_vvv, gen_helper_vor_v) +TRANS(vxor_v, gen_vvv, gen_helper_vxor_v) +TRANS(vnor_v, gen_vvv, gen_helper_vnor_v) +TRANS(vandn_v, gen_vvv, gen_helper_vandn_v) +TRANS(vorn_v, gen_vvv, gen_helper_vorn_v)
These can be implemented with tcg_gen_gvec_{and,or,xor,andc,orc,nor}.
+TRANS(vandi_b, gen_vv_i, gen_helper_vandi_b) +TRANS(vori_b, gen_vv_i, gen_helper_vori_b) +TRANS(vxori_b, gen_vv_i, gen_helper_vxori_b)
These are tcg_gen_gvec_{andi,ori,xori}.
+TRANS(vnori_b, gen_vv_i, gen_helper_vnori_b)
This would need dup + nor. r~
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