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[PULL 16/40] tests/tcg/arm: Manually register allocate half-precision nu
From: |
Alex Bennée |
Subject: |
[PULL 16/40] tests/tcg/arm: Manually register allocate half-precision numbers |
Date: |
Fri, 5 Jul 2024 16:30:28 +0100 |
From: Akihiko Odaki <akihiko.odaki@daynix.com>
Clang does not allow specifying an integer as the value of a single
precision register. Explicitly move value from a general register.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
[rth: Use one single inline asm block.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Message-Id: <20240630190050.160642-12-richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240705084047.857176-17-alex.bennee@linaro.org>
diff --git a/tests/tcg/arm/fcvt.c b/tests/tcg/arm/fcvt.c
index 157790e679..d8c61cd29f 100644
--- a/tests/tcg/arm/fcvt.c
+++ b/tests/tcg/arm/fcvt.c
@@ -355,7 +355,12 @@ static void convert_half_to_single(void)
print_half_number(i, input);
#if defined(__arm__)
- asm("vcvtb.f32.f16 %0, %1" : "=w" (output) : "x" ((uint32_t)input));
+ /*
+ * Clang refuses to allocate an integer to a fp register.
+ * Perform the move from a general register by hand.
+ */
+ asm("vmov %0, %1\n\t"
+ "vcvtb.f32.f16 %0, %0" : "=w" (output) : "r" (input));
#else
asm("fcvt %s0, %h1" : "=w" (output) : "w" (input));
#endif
--
2.39.2
- [PULL 13/40] tests/tcg/arm: Fix fcvt result messages, (continued)
- [PULL 13/40] tests/tcg/arm: Fix fcvt result messages, Alex Bennée, 2024/07/05
- [PULL 08/40] tests/tcg/aarch64: Drop -fno-tree-loop-distribute-patterns, Alex Bennée, 2024/07/05
- [PULL 09/40] tests/tcg/aarch64: Explicitly specify register width, Alex Bennée, 2024/07/05
- [PULL 15/40] tests/tcg/arm: Use -fno-integrated-as for test-arm-iwmmxt, Alex Bennée, 2024/07/05
- [PULL 17/40] tests/tcg/arm: Use -march and -mfpu for fcvt, Alex Bennée, 2024/07/05
- [PULL 37/40] gdbstub: Pass CPU context to command handler, Alex Bennée, 2024/07/05
- [PULL 35/40] target/arm: Factor out code for setting MTE TCF0 field, Alex Bennée, 2024/07/05
- [PULL 40/40] tests/tcg/aarch64: Add MTE gdbstub tests, Alex Bennée, 2024/07/05
- [PULL 11/40] tests/tcg/aarch64: Do not use x constraint, Alex Bennée, 2024/07/05
- [PULL 14/40] tests/tcg/arm: Drop -N from LDFLAGS, Alex Bennée, 2024/07/05
- [PULL 16/40] tests/tcg/arm: Manually register allocate half-precision numbers,
Alex Bennée <=
- [PULL 27/40] plugins: Ensure vCPU index is assigned in init/exit hooks, Alex Bennée, 2024/07/05
- [PULL 32/40] gdbstub: Add support for target-specific stubs, Alex Bennée, 2024/07/05
- [PULL 21/40] test/plugin: make insn plugin less noisy by default, Alex Bennée, 2024/07/05
- [PULL 29/40] accel/tcg: Move qemu_plugin_vcpu_init__async() to plugins/, Alex Bennée, 2024/07/05
- [PULL 34/40] target/arm: Make some MTE helpers widely available, Alex Bennée, 2024/07/05
- [PULL 25/40] plugins/lockstep: mention the one-insn-per-tb option, Alex Bennée, 2024/07/05
- [PULL 24/40] plugins/lockstep: make mixed-mode safe, Alex Bennée, 2024/07/05
- [PULL 23/40] plugins/lockstep: preserve sock_path, Alex Bennée, 2024/07/05
- [PULL 36/40] gdbstub: Make hex conversion function non-internal, Alex Bennée, 2024/07/05
- [PULL 39/40] gdbstub: Add support for MTE in user mode, Alex Bennée, 2024/07/05