Re: [PATCH 1/1] target/riscv: Remove redundant insn length check for zama16b

[Richard Henderson]

On 7/23/24 11:30, LIU Zhiwei wrote:
> Both trans_fld/fsd/flw/fsw and gen_load/store will never be a
> translation function for compressed instructions, thus we can
> remove instruction length check for them.
>
> Suggested-by: Alistair Francis <alistair.francis@wdc.com>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>

That is both false (trans_fld is used from trans_c_fld), and not the takeaway you should 
have gotten (the operation of "fld" should not depend on the encoding).

Perhaps FLD/FSD should depend on the ISA (RV32 vs RV64), but perhaps not.  I cannot tell 
because I don't see a specification for Zama16b in

  https://wiki.riscv.org/display/HOME/RISC-V+Specification+Status


r~