Re: [PATCH 1/1] target/riscv: Remove redundant insn length check for zama16b

[Alistair Francis]

On Tue, Jul 23, 2024 at 12:13 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 7/23/24 11:30, LIU Zhiwei wrote:
> > Both trans_fld/fsd/flw/fsw and gen_load/store will never be a
> > translation function for compressed instructions, thus we can
> > remove instruction length check for them.
> >
> > Suggested-by: Alistair Francis <alistair.francis@wdc.com>
> > Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
>
> That is both false (trans_fld is used from trans_c_fld), and not the takeaway 
> you should
> have gotten (the operation of "fld" should not depend on the encoding).
>
> Perhaps FLD/FSD should depend on the ISA (RV32 vs RV64), but perhaps not.  I 
> cannot tell
> because I don't see a specification for Zama16b in

It doesn't seem to depend on the ISA xlen.

The whole spec is just a simple one liner. Apparently that is an extension

https://github.com/riscv/riscv-profiles/blob/1fe6f65f130c219c761142e74742d2409c173c40/src/rva23-profile.adoc?plain=1#L176

Alistair

>
>    https://wiki.riscv.org/display/HOME/RISC-V+Specification+Status
>
>
> r~
>