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Re: [PATCH 1/1] target/riscv: Remove redundant insn length check for zam


From: LIU Zhiwei
Subject: Re: [PATCH 1/1] target/riscv: Remove redundant insn length check for zama16b
Date: Tue, 23 Jul 2024 13:29:41 +0800
User-agent: Mozilla Thunderbird


On 2024/7/23 10:11, Richard Henderson wrote:
On 7/23/24 11:30, LIU Zhiwei wrote:
Both trans_fld/fsd/flw/fsw and gen_load/store will never be a
translation function for compressed instructions, thus we can
remove instruction length check for them.

Suggested-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>

That is both false (trans_fld is used from trans_c_fld),
Yes. I will fix it later.
and not the takeaway you should have gotten (the operation of "fld" should not depend on the encoding

Do you mean c_fld 和fld both applies to zama16b?

).

Perhaps FLD/FSD should depend on the ISA (RV32 vs RV64), but perhaps not.  I cannot tell because I don't see a specification for Zama16b in

  https://wiki.riscv.org/display/HOME/RISC-V+Specification+Status

I think Zama16b first named in RVA23 profile as Alistair points out.

The more detailed information about its meaning is in priviledged 1.13 specification. More exactly, in 3.6.4. Misaligned Atomicity Granule PMA.

The specification said:

"The misaligned atomicity granule PMA applies only to AMOs, loads and stores defined in the base
ISAs, and loads and stores of no more than MXLEN bits defined in the F, D, and Q extensions. For an
instruction in that set, if all accessed bytes lie within the same misaligned atomicity granule, the
instruction will not raise an exception for reasons of address alignment, and the instruction will give
rise to only one memory operation for the purposes of RVWMO—i.e., it will execute atomically."

That's the reason why I do not apply zama16b to compressed instructions.

Thanks,
Zhiwei



r~

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