Re: [PATCH 1/1] target/riscv: Remove redundant insn length check for zama16b

[Richard Henderson]

On 7/24/24 16:32, LIU Zhiwei wrote:
> > However!  It does explicitly say "no more than MXLEN bits", which means that an RV32/ 
> > RV64 check is appropriate for FLD/FSD, since MXLEN may be less than 64.
> Yes.  That's true. Although I don't know why MXLEN is needed as F, D or Q don't depend on 
> MXLEN. We can implement D extension on RV32 CPU.

Implementation of D on RV32 does not mean that FLD/FST is atomic -- it can be implemented 
with two 32-bit loads/stores under the hood.


r~