[RFC PATCH 00/11] target/ppc: implement legacy address-swizzling MSR_LE support

[Mark Cave-Ayland]

This series is my attempt at reworking Gitlab issue #2661 [1] suitable for 
inclusion
upstream. In summary, older PPC designs include BLRM (Byte Lane Reverse and 
Munging)
logic [2] and in particular the CPU uses address swizzling to perform word 
swaps in
little-endian mode. The main changes I've made compared to the provided PoC 
patch is
to ensure that configurations where address swizzling is disabled are not 
penalised.

Patches 1-4 introduce general accessor functions gen_ld_tl() and gen_st_tl() 
for CPU
loads and stores, whilst patches 5-6 implement the basic address swizzling 
logic.
Patch 7 applies the address swizzle to translator_ldl() whilst patches 8-9 
apply the
swizzling logic to the load and store atomics. Patch 10 applies the swizzle to
gen_conditional_store() and finally patch 11 ensures that 
default_tcg_memop_mask is
set correctly when address swizzling is enabled.

The series boots the test ISO image provided in GitLab [1], however it is 
marked RFC
mainly for 2 reasons:

- Is there a better (i.e. more efficient) way to perform the swizzle?

- Which CPUs should have address swizzling little-endian mode enabled? I was 
unable to
  find a concise list of the relevant CPUs.

For testing purposes the address swizzling little-endian mode is hard-coded to 
enabled
in the need_addrswizzle_le() function introduced by patch 5 when MSR_LE is set.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>

[1]: https://gitlab.com/qemu-project/qemu/-/issues/2661
[2]: https://wiki.preterhuman.net/images/f/fc/Endian.pdf


Mark Cave-Ayland (11):
  target/ppc: introduce gen_ld_tl() function
  target/ppc: replace tcg_gen_qemu_ld_tl() with gen_ld_tl()
  target/ppc: introduce gen_st_tl() function
  target/ppc: replace tcg_gen_qemu_st_tl() with gen_st_tl()
  target/ppc: introduce need_addrswizzle_le() function
  target/ppc: introduce gen_addr_swizzle_le() function
  target/ppc: implement address swizzle for instruction translation
  target/ppc: implement address swizzle for gen_ld_atomic()
  target/ppc: implement address swizzle for gen_st_atomic()
  target/ppc: implement address swizzle for gen_conditional_store()
  target/ppc: update DisasContext default_tcg_memop_mask value

 target/ppc/translate.c                     | 262 ++++++++++++++++++---
 target/ppc/translate/fixedpoint-impl.c.inc |   4 +-
 2 files changed, 226 insertions(+), 40 deletions(-)

-- 
2.39.5