[RFC PATCH 05/11] target/ppc: introduce need_addrswizzle_le() function

[Mark Cave-Ayland]

This function determines whether the MSR_LE bit should be used to implement
little endian accesses using address swizzling, instead of reversing the
byte order.

(FIXME: which CPUs?)

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
 target/ppc/translate.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 4c47f97607..1211435039 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -208,6 +208,12 @@ struct DisasContext {
 #define DISAS_CHAIN        DISAS_TARGET_2  /* lookup next tb, pc updated */
 #define DISAS_CHAIN_UPDATE DISAS_TARGET_3  /* lookup next tb, pc stale */
 
+/* Return true iff address swizzling required */
+static inline bool need_addrswizzle_le(const DisasContext *ctx)
+{
+    return ctx->le_mode && true;
+}
+
 /* Return true iff byteswap is needed in a scalar memop */
 static inline bool need_byteswap(const DisasContext *ctx)
 {
@@ -2578,7 +2584,9 @@ static TCGv do_ea_calc_ra(DisasContext *ctx, int ra)
 static void gen_ld_tl(DisasContext *ctx, TCGv val, TCGv addr, TCGArg idx,
                       MemOp memop)
 {
-    tcg_gen_qemu_ld_tl(val, addr, idx, memop);
+    if (!need_addrswizzle_le(ctx)) {
+        tcg_gen_qemu_ld_tl(val, addr, idx, memop);
+    }
 }
 
 #define GEN_QEMU_LOAD_TL(ldop, op)                                      \
@@ -2619,7 +2627,9 @@ GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_UQ))
 static void gen_st_tl(DisasContext *ctx, TCGv val, TCGv addr, TCGArg idx,
                       MemOp memop)
 {
-    tcg_gen_qemu_st_tl(val, addr, idx, memop);
+    if (!need_addrswizzle_le(ctx)) {
+        tcg_gen_qemu_st_tl(val, addr, idx, memop);
+    }
 }
 
 #define GEN_QEMU_STORE_TL(stop, op)                                     \
-- 
2.39.5