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[RFC PATCH 04/11] target/ppc: replace tcg_gen_qemu_st_tl() with gen_st_t
From: |
Mark Cave-Ayland |
Subject: |
[RFC PATCH 04/11] target/ppc: replace tcg_gen_qemu_st_tl() with gen_st_tl() |
Date: |
Thu, 12 Dec 2024 15:14:05 +0000 |
To ensure that all memory stores are performed by gen_st_tl(), convert all
remaining users of tcg_gen_qemu_st_tl() with gen_st_tl().
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
target/ppc/translate.c | 10 +++++-----
target/ppc/translate/fixedpoint-impl.c.inc | 2 +-
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index bf94f3a5de..4c47f97607 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -2724,7 +2724,7 @@ static void glue(gen_, name##epx)(DisasContext *ctx)
\
gen_set_access_type(ctx, ACCESS_INT); \
EA = tcg_temp_new(); \
gen_addr_reg_index(ctx, EA); \
- tcg_gen_qemu_st_tl( \
+ gen_st_tl(ctx, \
cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \
}
@@ -2980,7 +2980,7 @@ static void gen_fetch_inc_conditional(DisasContext *ctx,
MemOp memop,
/* E.g. for fetch and increment bounded... */
/* mem(EA,s) = (t != t2 ? u = t + 1 : t) */
tcg_gen_movcond_tl(cond, u, t, t2, u, t);
- tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop);
+ gen_st_tl(ctx, u, EA, ctx->mem_idx, memop);
/* RT = (t != t2 ? t : u = 1<<(s*8-1)) */
tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t,
@@ -3045,7 +3045,7 @@ static void gen_ld_atomic(DisasContext *ctx, MemOp memop)
}
tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1,
cpu_gpr[(rt + 2) & 31], t0);
- tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop);
+ gen_st_tl(ctx, t1, EA, ctx->mem_idx, memop);
tcg_gen_mov_tl(dst, t0);
}
break;
@@ -3149,8 +3149,8 @@ static void gen_st_atomic(DisasContext *ctx, MemOp memop)
gen_ld_tl(ctx, t2, ea_plus_s, ctx->mem_idx, memop);
tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t);
tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2);
- tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop);
- tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop);
+ gen_st_tl(ctx, s, EA, ctx->mem_idx, memop);
+ gen_st_tl(ctx, s2, ea_plus_s, ctx->mem_idx, memop);
}
break;
default:
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc
b/target/ppc/translate/fixedpoint-impl.c.inc
index 717e3f122f..6b2265bd8f 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -35,7 +35,7 @@ static bool do_ldst(DisasContext *ctx, int rt, int ra, TCGv
displ, bool update,
ea = do_ea_calc(ctx, ra, displ);
mop ^= ctx->default_tcg_memop_mask;
if (store) {
- tcg_gen_qemu_st_tl(cpu_gpr[rt], ea, ctx->mem_idx, mop);
+ gen_st_tl(ctx, cpu_gpr[rt], ea, ctx->mem_idx, mop);
} else {
gen_ld_tl(ctx, cpu_gpr[rt], ea, ctx->mem_idx, mop);
}
--
2.39.5
- [RFC PATCH 00/11] target/ppc: implement legacy address-swizzling MSR_LE support, Mark Cave-Ayland, 2024/12/12
- [RFC PATCH 01/11] target/ppc: introduce gen_ld_tl() function, Mark Cave-Ayland, 2024/12/12
- [RFC PATCH 03/11] target/ppc: introduce gen_st_tl() function, Mark Cave-Ayland, 2024/12/12
- [RFC PATCH 04/11] target/ppc: replace tcg_gen_qemu_st_tl() with gen_st_tl(),
Mark Cave-Ayland <=
- [RFC PATCH 06/11] target/ppc: introduce gen_addr_swizzle_le() function, Mark Cave-Ayland, 2024/12/12
- [RFC PATCH 07/11] target/ppc: implement address swizzle for instruction translation, Mark Cave-Ayland, 2024/12/12
- [RFC PATCH 05/11] target/ppc: introduce need_addrswizzle_le() function, Mark Cave-Ayland, 2024/12/12
- [RFC PATCH 08/11] target/ppc: implement address swizzle for gen_ld_atomic(), Mark Cave-Ayland, 2024/12/12
- [RFC PATCH 11/11] target/ppc: update DisasContext default_tcg_memop_mask value, Mark Cave-Ayland, 2024/12/12
- [RFC PATCH 09/11] target/ppc: implement address swizzle for gen_st_atomic(), Mark Cave-Ayland, 2024/12/12