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[RFC PATCH 07/11] target/ppc: implement address swizzle for instruction
From: |
Mark Cave-Ayland |
Subject: |
[RFC PATCH 07/11] target/ppc: implement address swizzle for instruction translation |
Date: |
Thu, 12 Dec 2024 15:14:08 +0000 |
Ensure that the address swizzle is implemented when retrieving instructions from
guest memory for translation.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
target/ppc/translate.c | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index ddc0f85fb7..74aa398f25 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6600,7 +6600,11 @@ static void ppc_tr_translate_insn(DisasContextBase
*dcbase, CPUState *cs)
ctx->base.pc_next, ctx->mem_idx, (int)msr_ir);
ctx->cia = pc = ctx->base.pc_next;
- insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx));
+ if (!need_addrswizzle_le(ctx)) {
+ insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx));
+ } else {
+ insn = translator_ldl(env, dcbase, pc ^ 4);
+ }
ctx->base.pc_next = pc += 4;
if (!is_prefix_insn(ctx, insn)) {
@@ -6616,8 +6620,13 @@ static void ppc_tr_translate_insn(DisasContextBase
*dcbase, CPUState *cs)
gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN);
ok = true;
} else {
- uint32_t insn2 = translator_ldl_swap(env, dcbase, pc,
- need_byteswap(ctx));
+ uint32_t insn2;
+
+ if (!need_addrswizzle_le(ctx)) {
+ insn2 = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx));
+ } else {
+ insn2 = translator_ldl(env, dcbase, pc ^ 4);
+ }
ctx->base.pc_next = pc += 4;
ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn));
}
--
2.39.5
- [RFC PATCH 00/11] target/ppc: implement legacy address-swizzling MSR_LE support, Mark Cave-Ayland, 2024/12/12
- [RFC PATCH 01/11] target/ppc: introduce gen_ld_tl() function, Mark Cave-Ayland, 2024/12/12
- [RFC PATCH 03/11] target/ppc: introduce gen_st_tl() function, Mark Cave-Ayland, 2024/12/12
- [RFC PATCH 04/11] target/ppc: replace tcg_gen_qemu_st_tl() with gen_st_tl(), Mark Cave-Ayland, 2024/12/12
- [RFC PATCH 06/11] target/ppc: introduce gen_addr_swizzle_le() function, Mark Cave-Ayland, 2024/12/12
- [RFC PATCH 07/11] target/ppc: implement address swizzle for instruction translation,
Mark Cave-Ayland <=
- [RFC PATCH 05/11] target/ppc: introduce need_addrswizzle_le() function, Mark Cave-Ayland, 2024/12/12
- [RFC PATCH 08/11] target/ppc: implement address swizzle for gen_ld_atomic(), Mark Cave-Ayland, 2024/12/12
- [RFC PATCH 11/11] target/ppc: update DisasContext default_tcg_memop_mask value, Mark Cave-Ayland, 2024/12/12
- [RFC PATCH 09/11] target/ppc: implement address swizzle for gen_st_atomic(), Mark Cave-Ayland, 2024/12/12
- [RFC PATCH 10/11] target/ppc: implement address swizzle for gen_conditional_store(), Mark Cave-Ayland, 2024/12/12
- [RFC PATCH 02/11] target/ppc: replace tcg_gen_qemu_ld_tl() with gen_ld_tl(), Mark Cave-Ayland, 2024/12/12