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[RFC PATCH 03/11] target/ppc: introduce gen_st_tl() function
From: |
Mark Cave-Ayland |
Subject: |
[RFC PATCH 03/11] target/ppc: introduce gen_st_tl() function |
Date: |
Thu, 12 Dec 2024 15:14:04 +0000 |
This function is intended to be used for all memory store operations. Convert
the
GEN_QEMU_STORE_TL() macro to use it as a starting point.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
target/ppc/translate.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 5fb0aa36ce..bf94f3a5de 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -2616,12 +2616,18 @@ GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_UQ))
GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_UQ))
#endif
+static void gen_st_tl(DisasContext *ctx, TCGv val, TCGv addr, TCGArg idx,
+ MemOp memop)
+{
+ tcg_gen_qemu_st_tl(val, addr, idx, memop);
+}
+
#define GEN_QEMU_STORE_TL(stop, op) \
static void glue(gen_qemu_, stop)(DisasContext *ctx, \
TCGv val, \
TCGv addr) \
{ \
- tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
+ gen_st_tl(ctx, val, addr, ctx->mem_idx, op); \
}
#if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY)
--
2.39.5
- [RFC PATCH 00/11] target/ppc: implement legacy address-swizzling MSR_LE support, Mark Cave-Ayland, 2024/12/12
- [RFC PATCH 01/11] target/ppc: introduce gen_ld_tl() function, Mark Cave-Ayland, 2024/12/12
- [RFC PATCH 03/11] target/ppc: introduce gen_st_tl() function,
Mark Cave-Ayland <=
- [RFC PATCH 04/11] target/ppc: replace tcg_gen_qemu_st_tl() with gen_st_tl(), Mark Cave-Ayland, 2024/12/12
- [RFC PATCH 06/11] target/ppc: introduce gen_addr_swizzle_le() function, Mark Cave-Ayland, 2024/12/12
- [RFC PATCH 07/11] target/ppc: implement address swizzle for instruction translation, Mark Cave-Ayland, 2024/12/12
- [RFC PATCH 05/11] target/ppc: introduce need_addrswizzle_le() function, Mark Cave-Ayland, 2024/12/12
- [RFC PATCH 08/11] target/ppc: implement address swizzle for gen_ld_atomic(), Mark Cave-Ayland, 2024/12/12