I checked the simulator routine - it doesn't take into account the PRESET
and CLEAR inputs. It _does_ seem to try and simulate the normal behaviour
of the FF though.
I did a simpler circuit with only two FFs. The second has JK hanging from
the previous one's Q output. This should give a divide-by-4 circuit. I'm
guessing
there's something wrong with the order of the evaluation of things. I'm
guessing that for some reason the second JK always sees 1 on at least one
of the inputs.
Anyway - after a bit of experimenting something else went wrong: I get a
message:
Cannot find VHDL for test
When trying to run ASL sim. Where did that come from?