Re: Probably stupid problem...

[John Coppens]

On Tue, 24 Sep 2002 01:48:42 -0300
John Coppens <address@hidden> wrote:

> On Mon, 23 Sep 2002 15:52:17 -0700
> Steven Rubin <address@hidden> wrote:
> 
> > 
> > >I'm a first time user of Electric and made a very simple circuit with
> > >three JK FFs. I connected the JKs of the first to PWR, and the
> > >JKs of the second to the Q of the first. The JKs of the third
> > >go to an AND of Q0 and Q1. I believe this is the standard connection
> > >for a sync counter. Clocks are common.
> > >
> > >When simulating though, only the first JK acts normally (div 2).
> > >
> > >I've tried to connect the PRESET and CLR to 1 and 0 etc. I guess I'm
> > >missing something very basic here...
> > 
> > The implementation of FlipFlops is not complete in the built-in ALS 
> > simulator.  This is why some of them don't respond under simulation.  Check 
> > the VHDL and the netlist code to see more.
> 
> Hi Steven.
> 
> I checked the simulator routine - it doesn't take into account the PRESET
> and CLEAR inputs. It _does_ seem to try and simulate the normal behaviour
> of the FF though.
> 
> I did a simpler circuit with only two FFs. The second has JK hanging from
> the previous one's Q output. This should give a divide-by-4 circuit. I'm 
> guessing
> there's something wrong with the order of the evaluation of things. I'm
> guessing that for some reason the second JK always sees 1 on at least one
> of the inputs.
> 
> Anyway - after a bit of experimenting something else went wrong: I get a 
> message:
> 
>   Cannot find VHDL for test
> 
> When trying to run ASL sim. Where did that come from?

Sorry, had to call Make VHDL first. Can't remember having done this before,
but it solves the problem.

John